1. Field of the Invention
The present invention relates to a voltage-controlled oscillator oscillating a signal whose frequency corresponds to an input voltage thereto and a non-contact IC card including a voltage-controlled oscillator.
2. Description of the Prior Art
FIG. 9 is a circuit diagram showing a structure of a prior art voltage-controlled oscillator (VCO). Referring to FIG. 9, reference numeral 100 denotes a latch circuit comprising two inverter circuits 102 and 104, 200 denotes a P-channel transistor of which the gate is supplied with an input voltage VIN and the source is supplied with a power-supply voltage for example of 5V, 202 denotes a P-channel transistor of which the source is connected with the drain of the P-channel transistor 200, 203 denotes an N-channel transistor of which the drain is connected with the drain of the P-channel transistor 202 and the source is grounded, 220 denotes a capacitor of which one electrode is connected with the drain of the P-channel transistor 202 and the drain of the N-channel transistor 203 and the other electrode is grounded, 230 denotes a constant-current circuit, and 240 denotes a differential circuit comprising P-channel transistors 205 and 206 and N-channel transistors 207 and 208 and supplied with a power-supply voltage through the constant-current circuit 230. The gate of the P-channel transistor 205, which is one input of the differential circuit 240, is supplied with the voltage stored in the capacitor 220, and the gate of the P-channel transistor 206, which is the other input, is supplied with an internal power-supply voltage INTVCC. The internal power-supply voltage INTVCC is the reference voltage used within the VCO and its voltage is, for example, 1.7V. Reference numeral 209 denotes an N-channel transistor, of which the gate is connected with the output of the differential circuit 240 and the drain is connected with one input of the latch circuit 100, for inverting the latch data stored in the latch circuit 100.
Reference numeral 302 denotes a P-channel transistor of which the source is connected with the drain of the P-channel transistor 200, 303 denotes an N-channel transistor of which the drain is connected with the drain of the P-channel transistor 302 and the source is grounded, 320 denotes a capacitor of which one electrode is connected with the drain of the P-channel transistor 302 and the drain of the N-channel transistor 303 and the other electrode is grounded, 330 denotes a constant-current circuit, and 340 denotes a differential circuit including P-channel transistors 305 and 306 and N-channel transistors 307 and 308 and supplied with a power-supply voltage through the constant-current circuit 330. The gate of the P-channel transistor 305, which is one input of the differential circuit 340, is supplied with the voltage stored in the capacitor 320, and the gate of the P-channel transistor 306, which is the other input, is supplied with the internal power-supply voltage INTVCC. Reference numeral 309 denotes an N-channel transistor, of which the gate is connected with the output of the differential circuit 340 and the drain is connected with the other input of the latch circuit 100, for inverting the latch data stored in the latch circuit 100.
As apparent from FIG. 9, there are present two circuits of the same configurations between the latch circuit 100 and the P-channel transistor 200. The circuit configuration comprising circuit elements located from the P-channel transistor 202 and the N-channel transistor 203 to the N-channel transistor 209 will hereinafter be called the right circuit configuration. The circuit configuration comprising circuit elements located from the P-channel transistor 302 and the N-channel transistor 303 to the N-channel transistor 309 will hereinafter be called the left circuit configuration. The point C as one output point of the latch circuit 100 is connected with the gate of the P-channel transistor 302 and the gate of the N-channel transistor 303. The point D as the other output point of the latch circuit 100 is connected with the gate of the P-channel transistor 202 and the gate of the N-channel transistor 203. The signal at the point D becomes the output VCOOUT of the VCO through an inverter circuit 400.
Operations will be described below.
It is assumed that the VCO starts its operation, for example, when the capacitor 220 is in a discharged state and the capacitor 320 is in a charged state. Under these conditions, the potential at the point A as the output point of the differential circuit 240 is at a low (L) level and the N-channel transistor 209 is not turned on. On the other hand, the output of the differential circuit 340 is at a high (H) level and the N-channel transistor 309 is turned on. Since the N-channel transistor 309 is turned on, the level at the point D as the output point of the latch circuit 100 is L level and the level at the point C is H level.
Then, in the right circuit configuration, the P-channel transistor 202 is turned on and the N-channel transistor 203 is turned off, hence, a current corresponding to the input voltage VIN is supplied to the capacitor 220 through the P-channel transistor 200. Accordingly, the capacitor 220 is charged and the potential at the point B being the potential of the capacitor 220 rises. In the left circuit configuration, since the P-channel transistor 302 is turned off and the N-channel transistor 303 is turned on, the capacitor 320 is discharged.
When the potential at the point B exceeds the internal power-supply voltage INTVCC, the P-channel transistor 205, within the differential circuit 240, is turned off and the P-channel transistor 206 is turned on. Then, the potential at the point A as the output point of the differential circuit 240 rises and the N-channel transistor 209 is turned on. Hence, an L level develops at the drain of the N-channel transistor 209. Accordingly, the level at the point C as the output point of the latch circuit 100 goes to L level and the level at the point D goes to H level. Namely, the outputs of the latch circuit 100 are inverted.
Since the level at the point C has become L level, similar operations to those performed in the right circuit configuration as described above are performed in the left circuit configuration. Accordingly, after a predetermined period of time, the level at the point C as the output point of the latch circuit 100 goes to H level and the level at the point D goes to L level.
Since the above described operations are performed in the right circuit configuration and the left circuit configuration alternately, an oscillating signal as shown in FIG. 10 appears at the output VCOOUT. The cycle of inversion of the output of the latch circuit 100 depends on the charging and discharging time of the capacitors 220 and 320. The charging time of the capacitors 220 and 320 depends on the input voltage VIN applied to the gate of the P-channel transistor 200. When the input voltage VIN is low, the "on" current flowing through the P-channel transistor 200 increases and, hence, the charging time of the capacitors 220 and 320 becomes shorter. Conversely, when the input voltage VIN is high, the "on" current flowing through the P-channel transistor 200 decreases, hence, the charging time of the capacitors 220 and 320 becomes longer. Namely, when the input voltage VIN is low, the inverting cycle of the output of the latch circuit 100 becomes shorter, hence, the oscillation frequency becomes higher. Conversely, when the input voltage VIN is high, the inverting cycle of the output of the latch circuit 100 becomes longer, hence, the oscillation frequency becomes lower.
A VCO similar to the above described VCO is disclosed in JP-A 62/71332.
A non-contact IC card, as disclosed for example in JP-A 4/192091, is a card receiving a power carrier wave from an external source. In the non-contact IC card, power is extracted from an electric wave received from outside and a power-supply voltage for example of 5V is generated. Then, a clock signal is generated by means of a VCO or the like using the power-supply voltage and this clock signal is supplied to each circuit in the card. The external electric wave is not acceptable at all times. Only when communication is necessary can the external electric wave be accepted. Hence, the VCO in the non-contact IC card operates intermittently. Then, there sometimes occurs a case in which the VCO restarts its operation immediately after it has suspended its operation. In such a case, it sometimes occurs that the VCO restarts with charges remaining on both of the capacitors 220 and 320.
Namely, there arises such a case where both levels at the point B and the point E shown are H levels when the VCO has restarted. In such a case, since the outputs of both of differential circuits 240 and 340 become H level, both of the N-channel transistors 209 and 309 are turned on. Accordingly, the VCO starts with both of the levels at the points C and D as the output points of the latch circuit 100 pulled to L level. Then, since both of the P-channel transistors 202 and 302 are turned on, the potential at the point B and the point E rises further. That is, there arises such a case where both the point B and the point E are stabilized at H level, hence, the VCO is not able to oscillate.
Since the prior art voltage-controlled oscillator is structured as described above, there has been a problem that, when it is used for such an application in which it is possible that the VCO suspends operation with charges remaining on both capacitors 220 and 320 and then it immediately restarts under the same conditions, a stabilized oscillation cannot be obtained.